With the miniaturization of electronic products, there is a continuous need to reduce the size of devices and to add more functionality so that more IC devices can be accommodated area on a substrate. In prior IC device fabrication, an IC device has a foot print approximately the size of a die of the IC device. Multiple dies with multiple interconnection pads on each die are processed together to form a semiconductor wafer first. The devices that have been arrayed on the wafer are then packaged in many ways. Two such conventional packaging methods include separating the dies from the arrayed wafer prior to packaging, and packaging the arrayed dies on the semiconductor wafer while the arrayed dies are still in wafer form. After packaging, the arrayed dies are then separated, and the IC devices under conventional packaging methods are typically used in the desired application as a wafer level package device.
Referring to FIG. 1A-1F, different configurations are shown of prior wafer level package and chip scale packages of IC devices. FIG. 1A-1F show typical IC devices that are fabricated in conventional wafer level configurations. For example the IC wafer level package devices that are shown in FIG. 1A-1F have interconnects formed after wafer configuration. FIG. 1A shows solder interconnects 4 formed after layers 3 of functional devices and I/O 2 are formed on a wafer substrate 1. FIG. 1B shows holes 5 with conductive material that are processed for the I/O. FIG. 1C shows three dimensional connector for internally connecting backside with drilling to connect I/O pad. FIG. 1D shows I/O connector 7 along side wall after device fabrication. FIG. 1E shows holes processed like holes shown in FIG. 1B to connect I/O pad 8. FIG. 1F shows holes processed like holes shown in FIG. 1B with solder ball and wire bonding 9. Each individual device is packaged while the devices are still available in wafer form, prior to the wafer dicing process to obtain chip sized package. Many packaging process steps are added directly on a device wafer to realize these chip sized packages, which are of small form factor and reduced weight. However, the resulting IC device that is fabricated by the conventional processes is limited by I/O density as the chip size determines the package I/O density.
For example, U.S. Pat. Nos. 6,040,235 and 6,117,707 disclose two processes that are conventional. U.S. Pat. No. 6,040,235 discloses an IC device having a footprint approximately the size of a die of the IC device. The steps for manufacturing the IC device in such a conventional process includes providing a wafer that includes multiple dies wherein each die includes multiple connection pads; sandwiching the wafer between two protective layers; cutting notches through one of the protective layers along outlines of the dies to expose portions of the connection pads; forming metal contacts on the surface of the notched protective layer that are electrically connected to the exposed portions of the connection pads; and separating the dies to form individual dies. The step of cutting notches is sequential and therefore is time-consuming, and also requires an accurate fixed angular shaped cutting blade for cutting the notches. As cutting produces debris, the cutting step has to be performed outside of a clean room to prevent contamination and damage of the device. A cut wafer is then transported into the clean room for further processing, making handling of the wafer cumbersome. Additionally, the two protective layers on a resultant die also increase the cost of fabrication.
U.S. Pat. No. 6,117,707 discloses another IC device having multiple dies similar to that disclosed in U.S. Pat. No. 6,040,235. The dies are arranged in a stacked configuration. Interconnections between the dies of such an IC device are formed only after the stacks of dies are separated to form individualized IC devices. Accordingly, the process of interconnecting the dies in a device is performed on a device level and increases fabrication time.
The conventional fabricating methods disclose packaging/interconnection of the device IOs to the external system after the devices are pre-fabricated, which limits the number of IOs and functionality of device per square of silicon area. Also additional processes and packaging are required for routing of the interconnection lines across or within the chip to the IOs located peripherally around the chip to enable external interconnections. It is well known in the art of semiconductor industry that handling of devices once it is fabricated is a critical step. Risk involved in loosing wafer yields is highly dependent on the amount of handling and process stages the device wafer undergoes after the wafer reaches packaging and assembly houses.
Such conventional fabrication methods typically require additional device packaging methods after the devices are fabricated at the semiconductor wafer fabrication facilities which results in exposing the processed device to increased risk of contamination and damage. Therefore, there is a need for a method of fabricating a functional IC device that alleviates the problems associated with prior fabrication methods.